215 research outputs found

    Circuit Techniques for Low-Power and Secure Internet-of-Things Systems

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    The coming of Internet of Things (IoT) is expected to connect the physical world to the cyber world through ubiquitous sensors, actuators and computers. The nature of these applications demand long battery life and strong data security. To connect billions of things in the world, the hardware platform for IoT systems must be optimized towards low power consumption, high energy efficiency and low cost. With these constraints, the security of IoT systems become a even more difficult problem compared to that of computer systems. A new holistic system design considering both hardware and software implementations is demanded to face these new challenges. In this work, highly robust and low-cost true random number generators (TRNGs) and physically unclonable functions (PUFs) are designed and implemented as security primitives for secret key management in IoT systems. They provide three critical functions for crypto systems including runtime secret key generation, secure key storage and lightweight device authentication. To achieve robustness and simplicity, the concept of frequency collapse in multi-mode oscillator is proposed, which can effectively amplify the desired random variable in CMOS devices (i.e. process variation or noise) and provide a runtime monitor of the output quality. A TRNG with self-tuning loop to achieve robust operation across -40 to 120 degree Celsius and 0.6 to 1V variations, a TRNG that can be fully synthesized with only standard cells and commercial placement and routing tools, and a PUF with runtime filtering to achieve robust authentication, are designed based upon this concept and verified in several CMOS technology nodes. In addition, a 2-transistor sub-threshold amplifier based "weak" PUF is also presented for chip identification and key storage. This PUF achieves state-of-the-art 1.65% native unstable bit, 1.5fJ per bit energy efficiency, and 3.16% flipping bits across -40 to 120 degree Celsius range at the same time, while occupying only 553 feature size square area in 180nm CMOS. Secondly, the potential security threats of hardware Trojan is investigated and a new Trojan attack using analog behavior of digital processors is proposed as the first stealthy and controllable fabrication-time hardware attack. Hardware Trojan is an emerging concern about globalization of semiconductor supply chain, which can result in catastrophic attacks that are extremely difficult to find and protect against. Hardware Trojans proposed in previous works are based on either design-time code injection to hardware description language or fabrication-time modification of processing steps. There have been defenses developed for both types of attacks. A third type of attack that combines the benefits of logical stealthy and controllability in design-time attacks and physical "invisibility" is proposed in this work that crosses the analog and digital domains. The attack eludes activation by a diverse set of benchmarks and evades known defenses. Lastly, in addition to security-related circuits, physical sensors are also studied as fundamental building blocks of IoT systems in this work. Temperature sensing is one of the most desired functions for a wide range of IoT applications. A sub-threshold oscillator based digital temperature sensor utilizing the exponential temperature dependence of sub-threshold current is proposed and implemented. In 180nm CMOS, it achieves 0.22/0.19K inaccuracy and 73mK noise-limited resolution with only 8865 square micrometer additional area and 75nW extra power consumption to an existing IoT system.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/138779/1/kaiyuan_1.pd

    Nonuniform-spaced Critical Behavior of Dynamical Quantum Phase Transitions in Multi-band Bloch Hamiltonian

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    We investigate the dynamical quantum phase transition (DQPT) in the multi-band Bloch Hamiltonian of the one-dimensional periodic Kitaev model after a quench from a Bloch band. Our study goes beyond the limitations of previous works that primarily focused on two-band models and reveals significant differences in DQPT between the two-band and multi-band systems. Our results show that only the quench from the Bloch states, which causes the band gap to collapse at the critical point, induces the DQPT after crossing the quantum phase transition; otherwise, the DQPT will not occur. Additionally, the critical times of the DQPT are not evenly spaced due to the deviation in the critical momentum caused by the non-analytic singularities of the Pancharatnam geometric phase. Our findings provide a better understanding of the characteristics of non-equilibrium systems surrounding DQPTs.Comment: 9 pages, 10 figure

    Dynamics of the Geometric Phase in Inhomogeneous Quantum Spin Chains

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    The dynamics of the geometric phase are studied in inhomogeneous quantum spin chains after a quench. Analytic expressions of the Pancharatnam geometric phase (PGP) G(t)\mathcal{G}(t) are derived, for both the period-two quantum Ising chain (QIC) and the disordered QIC. In the period-two QIC, due to the periodic modulation, the PGP changes with time at the boundary of the Brillouin zone, and consequently, the winding number νD(t)=0π[ϕkG(t)/k]dk/2π\nu_{D}(t)=\int_{0}^{\pi}[\partial\phi_{k}^{G}(t)/\partial k]dk/2\pi based on the PGP is not quantized and thus not topological anymore. Nevertheless, the PGP and its winding number show non-analytic singularities at the critical times of the dynamical quantum phase transitions (DQPTs). This relation between the PGP and the DQPT is further confirmed in the disordered QIC, where the winding number is not defined. It is found that the critical time of DQPT inherited from the homogeneous system and the additional one induced by the weak disorder are also accompanied by the non-analytic singularity of the PGP, by decomposing the PGP into each quasiparticle mode. The connection between the non-analytic behavior of the PGP at the critical time and the DQPT, regardless of whether the winding number is topological, can be explained by the fact that they both arise when the Loschmidt amplitude vanishes.Comment: 14 pages, 8 figure

    Dominant Eigenvalue-Eigenvector Pair Estimation via Graph Infection

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    We present a novel method to estimate the dominant eigenvalue and eigenvector pair of any non-negative real matrix via graph infection. The key idea in our technique lies in approximating the solution to the first-order matrix ordinary differential equation (ODE) with the Euler method. Graphs, which can be weighted, directed, and with loops, are first converted to its adjacency matrix A. Then by a naive infection model for graphs, we establish the corresponding first-order matrix ODE, through which A's dominant eigenvalue is revealed by the fastest growing term. When there are multiple dominant eigenvalues of the same magnitude, the classical power iteration method can fail. In contrast, our method can converge to the dominant eigenvalue even when same-magnitude counterparts exist, be it complex or opposite in sign. We conduct several experiments comparing the convergence between our method and power iteration. Our results show clear advantages over power iteration for tree graphs, bipartite graphs, directed graphs with periods, and Markov chains with spider-traps. To our knowledge, this is the first work that estimates dominant eigenvalue and eigenvector pair from the perspective of a dynamical system and matrix ODE. We believe our method can be adopted as an alternative to power iteration, especially for graphs.Comment: 13 pages, 8 figures, 3 table

    Dynamical relaxation behavior of extended XY chain with gapless phase following a quantum quench

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    We investigate the dynamical relaxation behavior of the two-point correlation in extended XY models with a gapless phase after quenches from various initial states. Specifically, we study the XY chain with gapless phase induced by the additional interactions: Dzyaloshinskii-Moriya interaction and XZY-YZX type of three-site interaction. When quenching from the gapped phase, we observe that the additional interactions have no effect on the relaxation behavior. The relaxation behavior is δCmn(t)t3/2\delta C_{mn}(t)\sim t^{-3/2} and t1/2\sim t^{-1/2} for the quench to the commensurate phase and the incommensurate phase, respectively. However, when quenching from the gapless phase, we demonstrate that the scaling behavior of δCmn(t)\delta C_{mn}(t) is changed to t1\sim t^{-1} for the quench to the commensurate phase, and the decay of δCmn(t)\delta C_{mn}(t) follows t1\sim t^{-1} or t1/2\sim t^{-1/2} for the quench to the incommensurate phase depending on the parameters of pre-quench Hamiltonian. We also establish the dynamical phase diagrams based on the dynamical relaxation behavior of δCmn(t)\delta C_{mn}(t) in the extended XY models.Comment: 12 pages, 10 figure

    ASCH-PUF: A "Zero" Bit Error Rate CMOS Physically Unclonable Function with Dual-Mode Low-Cost Stabilization

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    Physically unclonable functions (PUFs) are increasingly adopted for low-cost and secure secret key and chip ID generations for embedded and IoT devices. Achieving 100% reproducible keys across wide temperature and voltage variations over the lifetime of a device is critical and conventionally requires large masking or Error Correction Code (ECC) overhead to guarantee. This paper presents an Automatic Self Checking and Healing (ASCH) stabilization technique for a state-of-the-art PUF cell design based on sub-threshold inverter chains. The ASCH system successfully removes all unstable PUF cells without the need for expensive temperature sweeps during unstable bit detection. By accurately finding all unstable bits without expensive temperature sweeps to find all unstable bits, ASCH achieves ultra-low bit error rate (BER), thus significantly reducing the costs of using ECC and enrollment. Our ASCH can operate in two modes, a static mode (S-ASCH) with a conventional pre-enrolled unstable bit mask and a dynamic mode (D-ASCH) that further eliminates the need for non-volatile memories (NVMs) for storing masks. The proposed ASCH-PUF is fabricated and evaluated in 65nm CMOS. The ASCH system achieves "0" Bit Error Rate (BER, < 1.77E-9) across temperature variations of -20{\deg}C to 125{\deg}C, and voltage variations of 0.7V to 1.4V, by masking 31% and 35% of all fabricated PUF bits in S-ASCH and D-ASCH mode respectively. The prototype achieves a measured throughput of 11.4 Gbps with 0.057 fJ/b core energy efficiency at 1.2V, 25{\deg}C.Comment: This paper has been accepted to IEEE Journal of Solid-State Circuits (JSSC
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